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? semiconductor components industries, llc, 2013 july, 2013 ? rev. 7 1 publication order number: CAT5132/d CAT5132 16 volt digital potentiometer (pot) with 128 taps and i 2 c interface description the CAT5132 is a high voltage digital pot with non-volatile wiper setting memory, operating like a mechanical potentiometer. the tap points between the 127 equal resistive elements are connected to the wiper output via cmos switches. the switches are controlled by a 7-bit wiper control register (wcr). the wiper setting can be stored in a 7-bit non-volatile data register (dr). the wcr is accessed via the i 2 c serial bus. upon power-up, the wcr is set to mid-scale (1000000). after the power supply is stable, the contents of the dr are transferred to the wcr and the wiper is returned to the memorized setting. the CAT5132 has two voltage supplies: v cc , the digital supply and v+, the analog supply. v+ can be much higher than v cc , allowing for 16 v analog operations. the CAT5132 can be used as a potentiometer or as a two-terminal variable resistor. features ? single linear digital potentiometer with 128 taps ? end-to-end resistance of 10 k , 50 k or 100 k ? i 2 c interface ? fast up/down wiper control mode ? non-volatile wiper setting storage ? automatic wiper setting recall at power ? up ? digital supply range (v cc ): 2.7 v to 5.5 v ? analog supply range (v+): +8 v to +16 v ? low standby current: 15 a ? 100 year wiper setting memory ? industrial t emperature range: ? 40 ? c to +85 ? c ? 10-pin msop package ? these devices are pb-free, halogen free/bfr free and are rohs compliant applications ? lcd screen adjustment ? volume control ? mechanical potentiometer replacement ? gain adjustment ? line impedance matching ? vcom setting adjustments http://onsemi.com pin configuration msop ? 10 z suffix case 846ae r h r l v+ scl a0 v cc gnd sda 1 (top view) r w a1 device package shipping ? ordering information CAT5132zi ? 10 ? gt3 msop (pb ? free) 3,000 / tape & reel CAT5132zi ? 50 ? gt3 CAT5132zi ? 00 ? gt3 marking diagram anbu = CAT5132zi-10-gt3 anbk = CAT5132zi-50-gt3 anbp = CAT5132zi-00-gt3 y = production year (last digit) m = production month (1-9, a, b, c) r = production revision anbx ymr ?for information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our tape and reel packaging specifications bro- chure, brd8011/d. 1. for detailed information and a breakdown of device nomenclature and numbering systems, please see the on semiconductor device no- menclature document, tnd310/d, available at www.onsemi.com . 2. the standard lead finish is nipdau. 3. for additional package and temperature options, please contact your nearest on semiconductor sales office.
CAT5132 http://onsemi.com 2 figure 1. block diagram sda scl control logic and address decode 7 ? bit wiper control register (wcr) (dr) v+ 127 resistive elements 127 0 a0 a1 v cc 7 ? bit nonvolatile memory register 128 tap position decode control r h r l r w table 1. pin function description pin no. pin name description 1 sda serial data input/output ? bidirectional serial data pin used to transfer data into and out of the CAT5132. this is an open-drain i/o and can be wire or?d with other open-drain (or open collector) i/os. 2 gnd ground 3 v cc digital supply voltage (2.7 v to 5.5 v) 4 a1 address select input to select slave address for i 2 c bus. 5 a0 address select input to select slave address for i 2 c bus. 6 r h high reference terminal for the potentiometer 7 r w wiper terminal for the potentiometer 8 r l low reference terminal for the potentiometer 9 v+ analog supply voltage for the potentiometer (+8.0 v to 16.0 v) 10 scl serial bus clock input for the i 2 c serial bus. this clock is used to clock all data transfers into and out of the CAT5132 table 2. absolute maximum ratings rating value unit temperature under bias ? 55 to +125 ? c storage temperature ? 65 to +150 ? c voltage on any sda, scl, a0 & a1 pins with respect to ground (note 4) ? 0.3 to v cc + 0.3 v voltage on r h , r l & r w pins with respect to ground v+ v cc with respect to ground ? 0.3 to +6 v v+ with respect to ground ? 0.3 to +16.5 v wiper current (10 sec) ? 6 ma lead soldering temperature (10 sec) +300 ? c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 4. latch-up protection is provided for stresses up to 100 ma on address and data pins from ? 0.3 v to v cc +0.3 v. table 3. recommended operating conditions rating value unit v cc +2.7 to +5.5 v v+ +8.0 to +16 v operating temperature range ? 40 to +85 ? c
CAT5132 http://onsemi.com 3 table 4. potentiometer characteristics (over recommended operating conditions unless otherwise stated.) symbol parameter test conditions limits units min typ max r pot potentiometer resistance (100 k ) 100 k r pot potentiometer resistance (50 k ) 50 k r pot potentiometer resistance (10 k ) 10 k r tol potentiometer resistance tolerance ? 20 % power rating 25 ? c 50 mw i w wiper current ? 3 ma r w wiper resistance i w = ? 1 ma @ v+ = 12 v 70 150 i w = ? 1 ma @ v+ = 8 v 110 200 v term voltage on r w , r h or r l gnd = 0 v; v+ = 8 v to 16 v gnd v+ v res resolution 0.78 % a lin absolute linearity (note 6) v w(n)(actual) ? v w(n)(expected) (notes 9, 10) ? 1 lsb (note 8) r lin relative linearity (note 7) v w(n+1) ? [v w(n) + lsb] (notes 9, 10) ? 0.5 lsb (note 8) tc rpot temperature coefficient of r pot (note 5) ? 300 ppm/ ? c tc ratio ratiometric temperature coefficient (note 5) 30 ppm/ ? c c h /c l /c w potentiometer capacitances (note 5) 10/10/25 pf fc frequency response r pot = 50 k 0.4 mhz 5. this parameter is tested initially and after a design or process change that affects the parameter. 6. absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 7. relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. 8. lsb = (r hm ? r lm )/127; where r hm and r lm are the highest and lowest measured values on the wiper terminal. 9. n = 1, 2, ..., 127 10. v + @ r h ; 0 v @ r l ; v w measured @ r w with no load. table 5. d.c. electrical characteristics (over recommended operating conditions unless otherwise stated.) symbol parameter test conditions min max units i cc1 power supply current (volatile write/read) f scl = 400 khz, sda open, v cc = 5.5 v, input = gnd 1 ma i cc2 power supply current (nonvolatile write) f scl = 400 khz, sda open, v cc = 5.5 v, input = gnd 3.0 ma i sb(vcc) standby current (v cc = 5 v) v in = gnd or v cc , sda = v cc 5 a i sb(v+) v+ standby current v cc = 5 v, v+ = 16 v 10 a i li input leakage current v in = gnd to v cc 10 a i lo output leakage current v out = gnd to v cc 10 a v il input low voltage ? 1 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 1.0 v v ol1 output low voltage (v cc = 3.0) i ol = 3 ma 0.4 v table 6. capacitance (t a = 25 ? c, f = 1.0 mhz, v cc = 5.0 v) symbol parameter test conditions min max units c i/o input/output capacitance (sda) v i/o = 0 v (note 11) 8 pf c in input capacitance (a0, a1, scl) v in = 0 v (note 11) 6 pf
CAT5132 http://onsemi.com 4 table 7. a.c. characteristics symbol parameter (see figure 6) v cc = 2.7 ? 5.5 v units min max f scl clock frequency 400 khz t i (note 11) noise suppression time constant at scl & sda inputs 50 ns t aa slc low to sda data out and ack out 1 s t buf (note 11) time the bus must be free before a new transmission can start 1.2 s t hd:sta start condition hold time 0.6 s t low clock low period 1.2 s t high clock high period 0.6 s t su:sta start condition setup time (for a repeated start condition) 0.6 s t hd:dat data in hold time 0 ns t r (note 11) sda and scl rise time 0.3 s t f (note 11) sda and scl fall time 300 ns t su:sto stop conditions setup time 0.6 s t dh data out hold time 100 ns 11. this parameter is tested initially and after a design or process change that affects the parameter. table 8. power up timing (notes 12, 13) symbol parameter min max units t pur power-up to read operation 1 ms t puw power-up to write operation 1 ms table 9. wiper timing symbol parameter min max units t wrpo wiper response time after power supply stable 5 10 s t wrl wiper response time after instruction issued 5 10 s table 10. write cycle limits symbol parameter min max units t wr write cycle time (see figure 7) 5 ms the write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. dur ing the write cycle, the bus interface circuits are disabled, sda is allowed to remain high and the device does not respond to its slave addr ess. table 11. reliability characteristics symbol parameter reference test method min max units n end (note 12) endurance mil ? std ? 883, test method 1033 100,000 cycles t dr (note 12) data retention mil ? std ? 883, test method 1008 100 years 12. this parameter is tested initially and after a design or process change that affects the parameter. 13. t pur and t puw are the delays required from the time vcc is stable until the specified operation can be initiated.
CAT5132 http://onsemi.com 5 typical performance characteristics figure 2. resistance between r w and r l figure 3. i cc 2 (nv write) vs. temperature tap position temperature ( ? c) 112 96 80 64 48 32 16 0 0 2 4 6 8 10 12 110 90 70 30 10 ? 10 ? 30 ? 50 0 50 100 200 250 300 350 400 figure 4. absolute linearity error per tap position figure 5. relative linearity error tap position tap position 112 96 80 64 48 32 16 0 ? 1.0 ? 0.8 ? 0.4 ? 0.2 0.2 0.4 0.8 1.0 112 96 80 64 48 32 16 0 ? 0.5 ? 0.4 ? 0.2 ? 0.1 0.1 0.2 0.4 0.5 r wl (k ) i cc 2 ( a) a lin error (lsb) a lin error (lsb) 128 50 130 150 v cc = 5.5 v v cc = 2.7 v 128 ? 0.6 0 0.6 t amb = 25 ? c r total = 10 k 128 t amb = 25 ? c r total = 10 k ? 0.3 0 0.3 v cc = 2.7 v; v+ = 8 v v cc = 5.5 v; v+ = 16 v v cc = 2.7 v; v+ = 8 v v cc = 5.5 v; v+ = 16 v v cc = 2.7 v; v+ = 8 v v cc = 5.5 v; v+ = 16 v
CAT5132 http://onsemi.com 6 figure 6. bus timing figure 7. write cycle timing scl sda in sda out condition address ack scl sda 8th bit byte n stop t wr condition start t buf t su:sto t su:dat t dh t r t low t low t high t hd:dat t aa t hd:sta t f t su:sta
CAT5132 http://onsemi.com 7 serial bus protocol the following defines the features of the i 2 c bus protocol: 1. data transfer may be initiated only when the bus is not busy. 2. during a data transfer, the data line must remain stable whenever the clock line is high. any changes in the data line while the clock is high will be interpreted as a start or stop condition. the device controlling the transfer is a master, typically a processor or controller, and the device being controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the CAT5132 will be considered a slave device in all applications. start condition the start condition precedes all commands to the device, and is defined as a high to low transition of sda when scl is high. the CAT5132 monitors the sda and scl lines and will not respond until this condition is met (see figure 8). stop condition a low to high transition of sda when scl is high determines the stop condition. all operations must end with a stop condition (see figure 8). acknowledge after a successful data transfer, each receiving device is required to generate an acknowledge. the acknowledging device pulls down the sda line during the ninth clock cycle, signaling that it received the 8 bits of data (see figure 9). the CAT5132 responds with an acknowledge after receiving a start condition and its slave address. if the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. when the CAT5132 is in a read mode it transmits 8 bits of data, releases the sda line, and monitors the line for an acknowledge. once it receives this acknowledge, the CAT5132 will continue to transmit data. if no acknowledge is sent by the master, the device terminates data transmission and waits for a stop condition. acknowledge polling the disabling of the inputs can be used to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the write operation, the CAT5132 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address. if the CAT5132 is still busy with the write operation, no ack will be returned. if the CAT5132 has completed the write operation, an ack will be returned and the host can then proceed with the next instruction operation. figure 8. start/stop condition sda scl start condition stop condition figure 9. acknowledge condition start scl from master ack setup ( ? t su:dat ) bus release delay (receiver) 9 8 ack delay ( ? t aa ) 1 data output from transmitter data output from receiver bus release delay (transmitter)
CAT5132 http://onsemi.com 8 device description access control register the volatile register wcr and the non-volatile register dr are accessed only by addressing the volatile access register ar first, using the 3 byte i 2 c protocol for all read and write operations (see t able 12). the first byte is the slave address/instruction byte (see details below). the second byte contains the address (02h) of the ar register. the data in the third byte controls which register wcr (80h) or dr (00h) is being addressed (see figure 10). slave address instruction byte description the first byte sent to the CAT5132 from the master processor is called the slave address byte. the most significant five bits of the slave address are a device type identifier. for the CAT5132 these bits are fixed at 01010 (refer to table 13). the next two bits, a1 and a0, are the internal slave address and must match the physical device address which is defined by the state of the a1 and a0 input pins. only the device with slave address matching the input byte will be accessed by the master. this allows up to 4 devices to reside on the same bus. the a1 and a0 inputs can be actively driven by cmos input signals or tied to v cc or ground. the last bit is the read/write bit and determines the function to be performed. if it is a ?1? a read command is initiated and if it is a ?0? a write is initiated. for the ar register only write is allowed. after the master sends a start condition and the slave address byte, the CAT5132 monitors the bus and responds with an acknowledge when its address matches the transmitted slave address. table 12. access control register 0 00000 st 1 1a00000010a asp 00000000 0 00000 st 1 1a00000010a asp 10000000 ack stop ack ack start id4 id3 id2 id1 id0 a1 a0 wb 1st byte 2nd byte ar address ? 02h 3rd byte wcr(80h) / dr(00h) selection table 13. byte 1 slave address and instruction byte device type identifier slave address id4 (msb) 0 id3 1 id2 0 id1 1 id0 0 a1 x a0 xx r/w read/write (lsb) figure 10. access register addressing using 3 bytes & instruction s c p p bus activity: master sda line s r t fixed variable ar register address k a c k a c k a t o s t a address slave wcr/dr selection
CAT5132 http://onsemi.com 9 wiper control register (wcr) description the CAT5132 contains a 7-bit wiper control register which is decoded to select one of the 128 switches along its resistor array. the wcr is a volatile register and is written with the contents of the nonvolatile data register (dr) on power-up. the wiper control register loses its contents when the CAT5132 is powered-down. the contents of the wcr may be read or changed directly by the host using a read/write command after addressing the wcr (see table 12 to access wcr). since the CAT5132 will only make use of the 7 lsb bits (the first data bit, or msb, is ignored) on write instructions and will always come back as a ?0? on read commands. a write operation (see table 14) requires a start condition, followed by a valid slave address byte, a valid address byte 00h, a data byte and a stop condition. after each of the three bytes the ca t5132 responds with an acknowledge. at this time the data is written only to volatile registers, then the device enters its standby state. table 14. wcr write operation 0 00000 st 1 1a00000010a asp 10000000 ack stop ack ack start id4 id3 id2 id1 id0 a1 a0 wb 1st byte 2nd byte ar address ? 02h 3rd byte wcr(80h) selection 0 00000 st 1 1a00000000a asp xxxxxxxx ack stop ack ack start slave address byte wcr address ? 00h data byte an increment operation (see table 15) requires a start condition, followed by a valid increment address byte (01011), a valid address byte 00h. after each of the two bytes, the CAT5132 responds with an acknowledge. at this time if the data is high then the wiper is incremented or if the data is low the wiper is decremented at each clock. once the stop is issued then the device enters its standby state with the wcr data as being the last inc/dec position. also, the wiper position does not roll over but is limited to min and max positions. table 15. wcr increment/decrement operation 0 00000 st 1 1a00000010a asp 10000000 ack stop ack ack start id4 id3 id2 id1 id0 a1 a0 wb 1st byte 2nd byte ar address ? 02h 3rd byte wcr(80h) selection 0 01000 st 1 1a00000000a sp 11110000 stop ack ack start slave address byte wcr address ? 00h increment (1) / decrement (0) bits a read operation (see table 16) requires a start condition, followed by a valid slave address byte for write, a valid address byte 00h, a second start and a second slave address byte for read. after each of the three bytes, the CAT5132 responds with an acknowledge and then the device transmits the data byte. the master terminates the read operation by issuing a stop condition following the last bit of data byte. table 16. wcr read operation 0 00000 st 1 1a00000010a asp 10000000 ack stop ack ack start id4 id3 id2 id1 id0 a1 a0 wb 1st byte 2nd byte ar address ? 02h 3rd byte wcr(80h) selection 0 00000 st 1 1a00000000 ack start slave address byte wcr address ? 00h 0 00001 st 1 1a0xxxxxxxsp stop start slave address byte data byte
CAT5132 http://onsemi.com 10 data register (dr) the data register (dr) is a nonvolatile register and its contents are automatically written to the wiper control register (wcr) on power-up. it can be read at any time without effecting the value of the wcr. the dr, like the wcr, only stores the 7 lsb bits and will report the msb bit as a ?0?. w riting to the dr is performed in the same fashion as the wcr except that a time delay of up to 5 ms is experienced while the nonvolatile store operation is being performed. during the internal non-volatile write cycle, the device ignores transitions at the sda and scl pins, and the sda output is at a high impedance state. the wcr is also written during a write to dr. after a dr write is complete the dr and wcr will contain the same wiper position. to write or read to the dr, first the access to dr is selected, see table 1 then the data is written or read using the following sequences. a write operation (see table 17) requires a start condition, followed by a valid slave address byte, a valid address byte 00h, a data byte and a stop condition. after each of the three bytes the ca t5132 responds with an acknowledge. at this time the data is written both to volatile and non-volatile registers, then the device enters its standby state. table 17. dr write operation 0 00000 st 1 1a00000010a asp 00000000 ack stop ack ack start id4 id3 id2 id1 id0 a1 a0 wb 1st byte 2nd byte ar address ? 02h 3rd byte dr(00h) selection 0 00000 st 1 1a00000000a asp xxxx xxxx ack stop ack ack start slave address byte dr address ? 00h data byte a read operation (see table 18) requires a start condition, followed by a valid slave address byte, a valid address byte 00h, a second start and a second slave address byte for read. after each of the three bytes the CAT5132 responds with an acknowledge and then the device transmits the data byte. the master terminates the read operation by issuing a stop condition following the last bit of data byte. table 18. dr read operation 0 00000 st 1 1a00000010a asp 00000000 ack stop ack ack start id4 id3 id2 id1 id0 a1 a0 wb 1st byte 2nd byte ar address ? 02h 3rd byte dr(00h) selection 0 00000 st 1 1a00000000 ack start slave address byte dr address ? 00h 0 00001 st 1 1a0xxxxxxxsp stop start slave address byte data byte
CAT5132 http://onsemi.com 11 potentiometer operation power-on the CAT5132 is a 128-position, digital controlled potentiometer. when applying power to the CAT5132, v cc must be supplied prior to or simultaneously with v+. at the same time, the signals on r h , r w and r l terminals should not exceed v+. if v+ is applied before v cc , the electronic switches are powered in the absence of the switch control signals, that could result in multiple switches being turned on. this causes unexpected wiper settings and possible current overload of the potentiometer. when v cc is applied the device turns on at the mid-point wiper location (64) until the wiper register can be loaded with the nonvolatile memory location previously stored in the device. after the nonvolatile memory data is loaded into the wiper register the wiper location will change to the previously stored wiper position. at power-down, it is recommended to turn-off first the signals on r h , r w and r l , followed by v+ and, after that, v cc , in order to avoid unexpected transmissions of the wiper and uncontrolled current overload of the potentiometer. the end-to-end nominal resistance of the potentiometer has 128 contact points linearly distributed across the total resistor. each of these contact points is addressed by the 7 bit wiper register which is decoded to select one of these 128 contact points. each contact point generates a linear resistive value between the 0 position and the 127 position. these values can be determined by dividing the end-to-end value of the potentiometer by 127. in the case of the 10 k potentiometer ~79 is the resistance between each wiper position. however in addition to the ~79 for each resistive segment of the potentiometer, a wiper resistance offset must be considered. table 19 shows the effect of this value and how it would appear on the wiper terminal. this of fset will appear in each of the ca t5132 end-to-end resistance values in the same way as the 10 k example. however resistance between each wiper position for the 50 k version will be ~395 and for the 100 k version will be ~790 . table 19. potentiometer resistance and wiper resistance offset effects position typical r w to r l resistance for 10 k digital pot 00 70 or 0 + 70 01 149 or 79 + 70 63 5,047 or 4,977 + 70 127 10,070 or 10,000 + 70 position typical r w to r h resistance for 10 k digital pot 00 10,070 or 10,000 + 70 64 5,047 or 4,977 + 70 126 149 or 79 + 70 127 70 or 0 + 70
CAT5132 http://onsemi.com 12 package dimensions msop 10, 3x3 case 846ae issue o e1 e a2 a1 e b d c a top view side view end view l1 l2 l detail a detail a notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-187. symbol min nom max a a1 a2 b c d e e1 e l 0o 8o l2 0.00 0.75 0.17 0.13 0.40 2.90 4.75 2.90 0.50 bsc 0.25 bsc 1.10 0.15 0.95 0.27 0.23 0.80 3.10 5.05 3.10 0.60 3.00 4.90 3.00 l1 0.95 ref 0.05 0.85 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 CAT5132/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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